1. Field of the Invention
The present invention relates to scan test apparatus for performing scan test of devices.
2. Description of the Related Art
Recently, it is difficult to perform operation test of device mounted boards or mounted devices because of high functions or high density mounting of devices. Especially, in-circuit testers are prohibitively expensive to do operation analysis. Scan test systems are used for scan designed devices such as those according to the architecture under IEEE Standard 1149.1a. They are able to check the operation of a specified device or each device by forming a scan pass in which scan flip-flops on the devices are connected with a scan chain to output from the connector output defect analysis information (hereinafter "scan data log").
In the conventional scan test systems, the contents of a scan data log are data outputted in response to a test pattern, which indicate the failure position with the address at which the failure takes place.
The above conventional scan test systems provide only data for the test pattern and the failure occurrence address and the following problems:
The information desired to obtain from the scan test includes:
(1) the scan chain where a failure takes place and PA1 (2) the scan flip-flop where a failure takes place. These pieces of information have been determined by using the test pattern, the historical information which shows how the test pattern is inputted, and the failure occurrence address. However, this operation requires large amounts of work and time.
The circuit design of devices includes computer simulation of the operation of designed circuits, scan test of the manufactured devices, and comparison between these results.
The computer simulation usually shows transitional conditions of the devices along the time axis. The conventional scan test systems provide only the failure occurrence address so that it is necessary to compare data at different parameters such as "address" and "time". Consequently, it is difficult to compare waveforms at a time, making failure analysis difficult.